This invention relates to a control circuit for a buck power factor correction (PFC) stage. Buck PFC stages are commonly used in high efficiency (90%+), low cost power converters. Typically, the buck PFC stage is designed in such a manner that the control loop for the PFC stage is very slow. For example, it is not uncommon for a buck PFC stage to be implemented with a crossover frequency of the order of 10 Hz to 20 Hz. Such a crossover frequency is necessary if appropriate power factor and line current harmonics performance are to be ensured, with contained current distortion over the line cycle.
However, there are problems with having such a slow control loop. For example, a slow loop response is incompatible with the need for a fast response required in addressing overvoltage conditions. One common requirement of many PFC stages is that a minimum duty-cycle condition is maintained. In the event of having to maintain a minimum duty-cycle during light load conditions, an overvoltage condition can occur quite readily.
It is an object of the present invention to provide a control circuit and a control methodology for a PFC stage that overcomes at least some of the problems with the known types of control circuits and methodologies. It is a further object of the present invention to provide a control circuit that achieves optimal light-load performance consistent with good harmonics performance at higher load conditions.